In the digital audio and telecommunications field, the high accuracy and high resolution digital-to-analog conversion (DAC) technology has become one of the key analog circuit technologies. Conventionally, either the weighted network circuit technique with trimming, or the multislope integration technique has been utilized for high resolution DAC's. In the weighted network, some trimming of the weighted network utilizing a laser, dynamic element matching, or the digital method utilizing Read-Only Memory (ROM), was required. This is due to the conversion accuracy, which depended in large part on the device matching tolerance of the weighted network. Typically, untrimmed weighted networks would yield a 14-bit accuracy, whereas the trimmed network could obtain a conversion accuracy of over 15-bits. In the multislope integration circuit technique, on the other hand, integrators, sample and hold circuits and current sources are required, which of necessity must be high speed devices with relatively high accuracy. High resolution DAC's utilizing this technology are difficult to realize due to the sample charge and the sample capacitor leaking through the base impedance of the transistors, which typically utilize bipolar technology.
Another technique that has come to the forefront in DAC technology is that utilizing oversampling conversion techniques. These are configured with a delta-sigma modulator in conjunction with conventional oversampling noise shaping techniques utilizing digital filters. Typically, an interpolation filter is utilized to increase the sample rate and then filter all images and quantization noise at f.sub.s /2 and above, f.sub.s being the input sampling frequency. The delta-sigma modulator receives the output of the interpolation filter and converts this oversampled signal to a one-bit data stream. This one-bit output controls a DAC, which has only two analog levels and, therefore, is inherently linear. This signal is then input to an analog low pass filter.
With the oversampling noise and shaping techniques utilized with high resolution DAC's, two problems have been recognized--DC Offset and Phase Linearity. The digital portion of the DAC comprising the interpolation filter, sample and hold circuit and the delta-sigma modulator can be designed such that they are substantially phase linear, and DC offset can also be provided. However, when the analog portion of the overall DAC system is implemented, i.e., the analog low pass filter, an additional level of DC offset may be introduced into the system in addition to a phase response non-linearity. It is very difficult to remove DC offset and provide a linear phase response in the analog portion of the DAC converter system. In applications such as digital audio, this DC offset and phase response linearity is audible and distracts from the high quality of audio that is desired. One solution to this problem has been to provide an offset register in the digital-to-analog converter, which offset represents the results of a calibration step. This offset is then summed during normal operation with a digital input to account for the various non-linearities that exist in the delta-sigma modulator. This is described in U.S. Pat. No. 5,087,914, filed Aug. 22, 1990, and entitled "DC Calibration System for a Digital-to-Analog Converter", which is incorporated herein by reference. This system utilizes a calibration control circuit that is operable to place the digital-to-analog converter into a calibration mode and, with a successive approximation controller, to generate an offset number. However, the successive approximation controller requires a large amount of circuitry and a completely separate block that is utilized only for calibration. Therefore, there exists a need for a more efficient calibration controller for calibrating a digital-to-analog converter.